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S6 - 记忆卡控制IC

 
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S 6 - 记忆卡控制IC
S6 - 记忆卡控制IC
Hyperstone S6记忆卡控制IC及其具备的韧体与应用程序,为适用MMC4.2SD 2.0界面的高可靠性与处理能力的记忆卡解决方式,提供了一个易于使用及一应俱全的解决方式及平台。
  • 取得专利的平均损耗算法(wear-leveling)技术与ECC技术,确保高可靠性与耐用度。
  • 最佳化32 Bit RISC 核心,指令集和韧体,适用于闪存处理技术。
  • 拥有DFA(Dual channel Direct Flash Access unit)技术,包含交错处理模式的暂存区。
  • 广大的暂存区,得以拥有最高的MLC处理效率。
  • 最低功耗设计,兼具节能功能。
  • 只需透过简单的韧体更新,不必更换硬件,即可拥有智能型与客制功能。
  • 附加的UART可连结如安全控制器(security controller)等外接装置。
  • ASSP不再需要外接稳压器,检测器或者二极管。
  • Turnkey solution包括韧体、治具、测试和研发硬件及SDMMC卡的参考电路。
主要应用
  • SecureDigitialTM - SD Cards for industrial and consumer applications
  • microSD cards for consumer and mobile applications
  • MultiMediaCardsTM (MMC)
  • eMMC embedded Flash
  • Multi-Chip-Packages (MCP)
  • SmartCards
产品信息
  • S6-LAK05 --- LGA 54, RoHS, -25 to +85 °C
  • S6-0ABD0 --- KGD / Wafer
兼容性及效能
  • Fully compliant to SD 1.01, 1.10, and 2.0 standards
  • Fully compliant to MMC 3.31, 4.1, and 4.2 standards
  • 2 times 4KB large page buffers achieving optimal performance for SLC and MLC flash chips with 4KB page size
  • Sustained read and write up to 24 and 23 MB/s respectively using SLC in SD mode
  • Sustained read and write up to 22 and 9 MB/s respectively using MLC in SD mode
  • Sustained read and write up to 42 and 25 MB/s respectively using SLC in MMC mode
  • Sustained read and write up to 42 and 9 MB/s respectively using MLC in MMC mode
  • Data transfer rate to flash-memory of up to 40MB/s per channel
中央处理单元
  • High performance 32-Bit Hyperstone RISC microprocessor
  • 10 to 60 MHz clock frequency using adjustable internal oscillator
  • 16 KB internal Boot ROM
  • 20 KB internal RAM
  • Card operation current of less than 25 mA
  • Automatic power-down mode during wait periods, power saving mode incl. automatic wake-up and sleep mode with Icc < 120 µA
  • Dual supply voltage 1.8V and 3.3V
  • On-chip voltage regulator for 1.8V and charge pump for 3.0V flash memory power supply
  • On-chip voltage regulator for 1.8V processor core supply
  • Internal voltage detector
  • Optimized die size, shape and pad layout for multi die packages and die stacking
主机接口与兼容性
  • Fully compliant to the SD 1.01, 1.10 and 2.0 (SDHC) standards
  • Fully compliant to MMC 3.31, 4.1 and 4.2 standards
  • Additional General Purpose UART and optional ISO 7816-3 interface
闪存接口与处理能力
  • Dual channel direct flash memory access (DFA)
  • Supporting all control signal for NAND type flash memory connection
  • Supporting direct connection of up to 4 flash memory chip enables (CE) - 2 per channel
  • 2 times 4KB large page buffers achieving optimal performance for SLC and MLC flash chips with 4KB page size
  • Flash memory power down logic and flash memory write protect control
  • Error Correcting Code (ECC) capable of correcting 4 symbols in a 512 Bytes sector with additional CRC
  • Supporting all current and future vendor flashes and technologies (NAND, AG-AND, MLC/SLC, NROM, ...) by firmware upgrades
  • Firmware storage in flash memory
  • Firmware is loaded into internal memory by the boot ROM
  • Flash management including mapping of logical block addresses (LBA) to corresponding physical block addresses (PBA)
  • Bad Block Management
  • Wear leveling
  • Power Loss Protection
  • Interleaving, cache, and multi-plane programming
    ... and many more