Based on an architecture from Hyperstone, the EI-32x core combines a 32-bit Risc core with a 16 to 32-bit fixed point DSP using an integrated instruction set to provide a unified programming model. The 32-bit wide 96-way register set supports parallel operations of the ALU, DSP and load-store units, delivering 2.4Gop/W. The 8kbyte of on-chip DRAM runs at CPU clock speed. Operating at 108MHz, power consumption is 180mW at 3.3V. On-chip peripheral support includes DRAM controller, software programmable PLL, 32-bit timer, three serial I/O lines, interrupt controller and a 16 to 32-bit bus interface addressing 4Gbyte of memory. It has power-down and sleep modes. Power-down halts instruction execution, while DRAM refresh and the internal timer are maintained, Sleep stops everything, drawing 30 µA until a wake-up signal is received.
electronics WEEKLY no. 1961