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The insights from the project are being applied to network processing, where the need to accelerate Internet Protocol processing is critical.
Part of a 30-month project known as The Protocol Processor Project, or Pro3 (www.pro3-processor.com), the work has demonstrated that typically only a small part of the Internet Protocol is active for more than 95 percent of the total processing time.
The partners in the Pro3 project, which is due to run to mid-2002, include RISC chip vendor Hyperstone AG (Konstanz, Germany), the Interuniversities Microelectronics Research Center (Imec, Leuven, Belgium) and Lucent Technologies Nederland BV (Huizen, Netherlands). The Pro3 project is part of the European Commission-funded Information Society Technologies collaborative research program.
The aim is to design a chip that can put the most active 10 percent of the protocol into reconfigurable hardware. Other parts of the protocol will be run on a Hyperstone processor core. The IP-accelerating hardware is expected to reconfigure to best support the most active instructions and associated tasks at run time under control from the RISC host.
To link the two parts of the design, Hyperstone is building a custom interface from its RISC processor to the reconfigurable section so that it can be controlled by instructions issued from the core. The company has used a similar approach to add DSP instructions into its RISC pipeline.
"We have some instruction codes reserved," said Matthias Steck, vice president of sales & marketing for Hyperstone. "They can be routed to the reconfigurable engine." Each instruction will be used to index into a memory that contains the configuration data for the reconfigurable logic that can service that instruction.
Reconfigurable memory
"Imec will contribute a novel memory architecture tuned for reconfigurable architectures. They have some ideas on how to design a memory for reconfigurability," said Steck. He added it would contain pipelining logic to boost performance. "The result of the project will be a test chip; then we will decide if it can be turned into a product. We expect the test chip to be ready by the end of next year or by the first quarter of 2002."
Lucent will build the test chip in 0.35 micron. Before that, the team expects to build an FPGA-based design as an intermediate proof of concept.
TechWeb.com
Part of a 30-month project known as The Protocol Processor Project, or Pro3 (www.pro3-processor.com), the work has demonstrated that typically only a small part of the Internet Protocol is active for more than 95 percent of the total processing time.
The partners in the Pro3 project, which is due to run to mid-2002, include RISC chip vendor Hyperstone AG (Konstanz, Germany), the Interuniversities Microelectronics Research Center (Imec, Leuven, Belgium) and Lucent Technologies Nederland BV (Huizen, Netherlands). The Pro3 project is part of the European Commission-funded Information Society Technologies collaborative research program.
The aim is to design a chip that can put the most active 10 percent of the protocol into reconfigurable hardware. Other parts of the protocol will be run on a Hyperstone processor core. The IP-accelerating hardware is expected to reconfigure to best support the most active instructions and associated tasks at run time under control from the RISC host.
To link the two parts of the design, Hyperstone is building a custom interface from its RISC processor to the reconfigurable section so that it can be controlled by instructions issued from the core. The company has used a similar approach to add DSP instructions into its RISC pipeline.
"We have some instruction codes reserved," said Matthias Steck, vice president of sales & marketing for Hyperstone. "They can be routed to the reconfigurable engine." Each instruction will be used to index into a memory that contains the configuration data for the reconfigurable logic that can service that instruction.
Reconfigurable memory
"Imec will contribute a novel memory architecture tuned for reconfigurable architectures. They have some ideas on how to design a memory for reconfigurability," said Steck. He added it would contain pipelining logic to boost performance. "The result of the project will be a test chip; then we will decide if it can be turned into a product. We expect the test chip to be ready by the end of next year or by the first quarter of 2002."
Lucent will build the test chip in 0.35 micron. Before that, the team expects to build an FPGA-based design as an intermediate proof of concept.
TechWeb.com
